The present invention relates to a data buffer control circuit and, particularly, to an interface arranged between a CPU and a low speed device under the data bus control of the CPU.
FIG. 1 shows an example of a conventional control circuit for this purpose, which corresponds to FIGS. 4-15 of "Intel: APX 286 Hardware Reference Manual 1983".
The conventional control circuit shown in FIG. 1 includes a data bus buffer 1, a data transfer/receive (DT/R) signal line 2 for transmitting a DT/R signal which is supplied to a direction (DIR) signal input of the data bus buffer 1 for determining the direction of data flow, a flip-flop circuit 3 including a pair of series connected flip-flops for temporarily storing the DT/R signal, a clock signal line 4 for supplying a timing reference signal to the flip-flop circuit 3, a data enable (DEN) signal line 5 for indicating whether the CPU (not shown) is performing a reading or writing operation, a bus select signal line 6 for indicating that the data bus buffer 1 is selected, and a control logic circuit 7 composed of NAND gates 71 and 72 and responsive to the signals from the DT/R signal line 2, the flip-flop circuit 4, the DEN signal line 5, and the bus select signal line 6 to produce a data bus buffer output enable (OE) signal. The DT/R signal line 2, the flip-flop circuit 3, the clock signal line 4, the DEN signal line 5, the bus select signal line 6, and the control logic circuit 7 constitute a data bus buffer control circuit 8.
In operation, when the CPU is in a read condition, i.e., the DT/R signal is in the "0" state, the control logic circuit 7 controls the output of the data bus buffer 1 according to outputs of the DEN signal line 5 and the bus select signal line 6. That is, since a logic "0" signal is supplied to the DIR input of the data bus buffer 1 and the DT/R signal line connected to one input of the NAND gate 71 is at the "0" level, the output of the NAND gate 71 is "1". Therefore, all of the inputs of the NAND gate 72 are "1", and thus it provides a "0" output. Consequently, the OE signal is supplied to the OE input of the data bus buffer 1, which connects the data to the CPU data bus. On the other hand, when the CPU is in a write condition, i.e., when the DT/R signal is "1", the output period of the data bus buffer 1 is restricted by the output of the flip-flop 3 which stores the preceding bus condition. The flip-flop 3 stores the condition of the previous DT/R signal 2 for 2 clocks and, when the stored condition is the read condition, the output of the NAND gate 71, rather than the NAND gate 72, is "0" during the period of the initial two clocks of the write cycle, even when the signals on the DEN signal line 5 and the bus select signal line 6 are effective. Therefore the output of the data bus buffer 1 is not enabled. Thus, coincidence of floating data which is read out of the read device immediately after the read cycle and write data outputted from the CPU through the data bus buffer during the write period on the local bus can be avoided.
The conventional data bus buffer control circuit employs a fixed number of clock periods for which the write data output immediately after the read cycle is delayed (in the example in FIG. 1, the delay corresponds to two clock periods) and, therefore, it is not always possible to suitably delay the write data output to be supplied to devices operating at various speeds. Further, since the flip-flop simply stores the preceding cycle, it is impossible to provide a delay beyond three clock periods, even if the number of flip-flop stages is increased, and thus it is impossible to access a device whose floating period of read data is long.